1. Field of the Invention
The present invention relates to a method of fabricating a metal-oxide-semiconductor (MOS) transistor, and more particularly, to a method of fabricating a MOS transistor with a recessed channel.
2. Description of Related Art
As the size of semiconductor devices continues to reduce, short channel effect in a conventional planar metal-oxide-semiconductor (MOS) transistor is often intensified due to a reduction in channel length so that the device is prevented from operating normally. Therefore, as the channel length is reduced, the amount of dopants within the channel is often increased to minimize the short channel effect. However, excess dopants in the channel lead to another problem, namely, an increase in the leakage current.
As a result, MOS transistor having a recessed channel has been developed. The recessed channel not only reduces the size of the device, but also effectively increases the channel length and improves the short channel effect.
Although a recessed channel in the MOS transistor can improve short channel effect, the MOS transistor with a recessed channel has a larger gate-to-drain overlap region when compared with a conventional planar MOS transistor.
In general, a larger gate-to-drain overlap region causes a gate-induced drain leakage (GIDL) current, thereby increasing the standby current. In addition, when the MOS transistor with a recessed channel is applied to a dynamic random access memory, the gate-induced drain leakage current results in a lowering of the retention time of the dynamic random access memory. On the other hand, the capacitance produced by the larger gate-to-drain overlap region causes an increase in gate delay as well as a lowering of device speed.